Large capacity, small size, and low standby current are demanded of memory installed in portable devices. Even though it is a characteristic that the standby current of an SRAM is one order of magnitude or smaller than that of a DRAM, the area of a memory cell is larger than that of a DRAM. It is therefore difficult to meet the demand of miniaturization.
Therefore, realization of an increase in capacity and a reduction in size was examined by applying a memory cell composed of four MOS transistors to the SRAM. However, there is a problem that the standby current increases because a memory cell consisting of four MOS transistors has to store the data using an off current of the MOS transistor.
The following is the prior art to solve this problem.
US 2003/0032250 discloses a technique for reducing the leakage current of a memory cell in the standby mode in an SRAM having a memory cell comprising two PMOS transistors as access MOS transistors and two NMOS transistors as drive MOS transistors.
U.S. Pat. No. 6,212,124 discloses a circuit technique to realize the retention of storage data and the reduction in leakage current in an SRAM having a memory cell comprising two PMOS transistors as access MOS transistors and two NMOS transistors as drive MOS transistors by controlling the word line voltage of the non-selected memory cell.
US2002/51379 discloses a technique for ensuring stability in read mode in an SRAM having a memory cell comprising two PMOS transistors as access MOS transistors and two NMOS transistors as drive MOS transistors by controlling the word line voltage of the selected memory cell in read mode to be smaller than 90% of the power-supply voltage.
FIG. 13 illustrates a configuration of memory cell MC comprising the PMOS transistors (MP1 and MP2) as the access MOS transistors and NMOS transistors (MN1 and MN2) as the drive MOS transistors. Each gate of PMOS transistors MP1 and MP2 is connected to the word line WL. The source of PMOS transistor MP1 is connected to one (BT) of the bit line pairs (BT and BB), and the drain is connected to one of the storage nodes NL. On the other hand, the source of PMOS transistor MP2 is connected to another (BB) of the bit line pairs (BT and BB), and the drain is connected to another of the storage nodes NR. The drain of NMOS transistor MN1 and the gate of NMOS transistor MN2 are connected to the storage node NL. On the other hand, the drain of NMOS transistor MN2 and the gate of NMOS transistor MN1 are connected to the storage node NR. Each source of NMOS transistor MN1 and MN2 is connected to, for example, the ground voltage VSS of 0 V. The data of one bit are retained by holding one of the storage node pairs (NL and NR) of the memory cell MC to H (High) level and another to L (Low) level.
Next, a means of data retention of the memory cell MC shown in FIG. 13 will be explained. In this embodiment, it is assumed that the storage node NL is in the H level and the storage node NR is in the L level. The memory cell maintains the charge of the storage node NL which is in the H level using the leakage current IOFF(P) in the off mode of PMOS transistor MP1. Therefore, in the standby mode (in data retention mode), the power-supply voltage VDD (>VSS) is supplied to both the word line WL and the bit line pair (BT and BB). Thereby, the PMOS transistors MP1 and MP2 become OFF mode, and the power-supply voltage VDD is supplied through the bit line pair (BT and BB) to each of the drains of PMOS transistors MP1 and MP2 in off mode. The leakage current IOFF(P) of the PMOS transistor MP1 is controlled to be greater than the sum of the leakage current IOFF(N) of NMOS transistor MN1 in the off mode and the leakage current IG(N) of NMOS transistor MN2 in the on mode, thereby supplying a current (leakage current IOFF(P)) from the bit line BT to the storage node NL through the PMOS transistor MP1 and maintaining the H level (VDD). Moreover, the storage node NR is kept in the L level (VSS) by keeping the NMOS transistor MN2 in the on mode, the gate of which is connected to the storage node. As a result, the charge is retained in standby mode, and the data of one bit are stored.
As above described, even though there is a deviation in threshold voltage of the MOS transistor, in order to store the data in the memory cell, it is necessary that the leakage current IOFF(P) of the PMOS transistors (MP1 and MP2) be controlled to be greater than the sum of the leakage current IOFF(N) of the NMOS transistors (MN1 and MN2) and the leakage current IG(N). Moreover, the leakage current IOFF(P) of the PMOS transistors (MP1 and MP2) is preferably to be small, because the data retention current is determined according to the leakage current IOFF(P).
As a means of reducing the leakage current IOFF(P), the patent document 1 discloses a technique in which the thickness of the gate oxide film of the NMOS transistors (MN1 and MN2) is made thicker than the thickness of the gate oxide film of the PMOS transistors (MP1 and MP2). However, there are the following problems with this means.
The gate tunneling current of a MOS transistor increases with microfabrication. Therefore, it is necessary to increase the ratio of the thicknesses of the gate oxide films of NMOS transistor (MN1 and MN2) and PMOS transistor (MP1 and MP2) during microfabrication. As a result, the ratio of the current drivabilities of the NMOS transistor (MN1 and MN2) and the PMOS transistor (MP1 and MP2) (hereinafter called the cell ratio) becomes smaller.
Moreover, variations in processing, fluctuations in channel impurity concentration, and the deviation of the MOS transistor threshold voltage increase with microfabrication. Therefore, in order to keep the data retention current small, it is necessary to increase the threshold voltage of the NMOS transistors (MN1 and MN2). As a result, the cell ratio becomes smaller.
FIG. 14 shows a simulated result of the relationship between the storage node voltage and the cell ratio in read mode. Here, the simulation was carried out assuming that L level is kept in the storage node NR. As shown in FIG. 14, it is clear that the voltage of the storage node increases with decreasing cell ratio. Accordingly, the drive MOS transistor MN1 carries a current corresponding to the voltage of the storage node NR. As a result, two drive MOS transistors (MN1 and MN2) carry the current, resulting in increasing power consumption and decreasing the reading current. Moreover, in the worst case, the storage data might be destroyed.
In the case when the data retention current does not create a problem, a means of increasing the leakage current flowing in the PMOS transistors (MP1 and MP2) may be acceptable. However, the following problems arise when increasing IOFF(P) As described in the patent document 4, the reading current flowing in the access memory cell MC decreases by the leakage current IOFF(P) flowing in the non-access memory cell MC in read mode. In the worst case, it would be impossible to read the data. As described in U.S. Pat. No. 6,259,623 (JP-A No. 6370/2001), this problem can be solved by decreasing the number of memory cells MC connected to the bit line pair (BT and BB). However, a decrease in the number of memory cells MC connected to the bit line pair (BT and BB) brings an increase in the area of a chip, consequently, the chip area reduction effects of a four-transistor memory cell MC configuration are lost.